In many types of logic and computer circuits, it is desired to have circuit means for delaying a data stream of binary digital bits. A circuit device for accomplishing this purpose commonly is a shift register circuit. Such a shift register circuit is typically composed of one or more successive stages, the data stream being delayed by the same amount of time in each stage of the circuit. Of particular current interest are such circuits in N-MOS technology; that is, circuits formed with N-channel Metal Oxide Semiconductor transistors.
A useful shift register stage in prior art N-MOS technology has taken the form shown in FIG. 1, in which N-MOS transistors T.sub.2 and T.sub.4 are connected as "loads", T.sub.1 and T.sub.3 as "drivers", and in which .phi..sub.1 and .phi..sub.2 denote non-overlapping clock pulse voltage sequences; that is, only one (or none) of the sequences can be "high" at any instant of time. By "high" is meant that the pulse is of positive polarity sufficient to turn "on" an N-MOS transistor when the pulse is applied to the gate electrode of the transistor. By "low" is meant a pulse of lower positive voltage level (typically zero) than that corresponding to "high", sufficient to turn "off" the transistor.
In the shift register stage shown in the circuit of FIG. 1, an input signal V.sub.in ("high" or "low") subsequently appears as an output signal V.sub.out ("high" or "low"). More specifically, when a first clock pulse sequence .phi. goes "high", node N.sub.1 also goes "high" regardless of V.sub.in, because T.sub.2 goes "on" regardless of V.sub.in. When .phi..sub.1 thereafter goes "low", N.sub.1 goes "low" if and only if V.sub.in is then "high" and thus T.sub.1 is "on", because then transistor T.sub.2 is "off". A second clock pulse sequence, .phi..sub.2, non-overlapping with respect to the first is applied to the serially connected source-drain paths of transistors T.sub.3 and T.sub.4. Thus, after .phi..sub.2 subsequently goes "high" and then "low", node N.sub.2 or V.sub.out then is "high" or "low" depending upon whether transistor T.sub.3 is "off" or "on", respectively; that is, depending upon whether node N.sub.1 is then "low" or "high", respectively, in turn depending upon whether V.sub.in was "high" or "low". Accordingly, V.sub.out during the "low" phase of .phi..sub.2 represents the same binary state as V.sub.in represented during the "low" phase of .phi..sub.1 ; and V.sub.out remains constant at this value until the next succeeding "low" phase of .phi..sub.2.
The circuit shown in FIG. 1 thus effectuates an inversion of signal during each half-stage; that is to say, during the "low" phase of .phi..sub.1 the signal at node N.sub.1 is of the opposite polarity to that of the input signal V.sub.in. In some application, however, such inversions may not be desired because of time delays associated with such inversions which limit the speed of operation. On the other hand, the shift register stage shown in FIG. 1 has the advantageous properties that it requires only four transistors and only one constant voltage (such as V.sub.SS) access line. Moreover, the circuit shown in FIG. 1 has the disadvantage that in the case of a steady "low" input level (that is, a "low" level of input signal extending in time steadily over more than one clock cycle) the output is not a steady "low" level but goes to a "high" level during every "high" phase of .phi..sub.2.